Built-in self-testing (BIST) state machines are effective for testing a variety of integrated circuit (IC) components. BIST state machines for random access memories (RAMs) embedded with in an IC are created with a high degree of flexibility using a small silicon area. BIST state machines perform a variety of test suites. Test suites often include a wide array of industry standard tests, such as Scan, Mats+, MarchC, Partial MovI, and Hammer 10 tests. These tests each have unique features to find failures in memory cells, such as stuck-at faults, bridging, opens, excessive leakage, bit-line coupling, and address decoder faults.
Currently, BIST state machines use nineteen state machines to conduct a limited number of tests. Each state is limited to one operation. For example, one test that is commonly performed is a test called Mats++, illustrated in the flowchart of FIGS. 1a-b. Mats++ is a test useful in detecting stuck-at faults and address decode faults. Each memory is divided into cells, containing an array of addresses. As shown in FIG. 1a, the Mats++ begins (Block 100) by writing a solid background of data to the cell being tested (Block 105). In one embodiment, a solid background of data is written by setting each bit at the address to 0. The address block is set to the beginning X and Y coordinates, or (0,0), of the cell (Block 110). A read operation (Block 115) and an inverse write operation (Block 120) are performed as the address coordinates are incremented (Blocks 130 and 140) until the maximum coordinates in the address block are reached (as tested by Blocks 125 and 135). As illustrated in FIG. 1b, the address coordinates are then set at the maximum for both the X and Y coordinates (Block 145). An inverse read operation (Block 150), write operation (Block 155), and read operation (Block 160) are performed as the address coordinates are decremented (Blocks 170 and 180) until the maximum coordinates in the cell are reached, then the test is completed (Block 185).
A state machine, such as the one shown in the diagram of FIG. 2, can be used to implement the Mats++ test. The state machine includes an idle state (200) to which the state machine returns between test cycles and while tests are not being run. For the initial cycle in which a solid background is written, a first state (210) performs a looping write operation. With each write operation, the address is incremented until the entire memory cell has data written into it. For the second cycle, a second state (220) performs a looping read/write operation, in which data is read from an address, and then the inverse of that data is written back to the address. Again, the address is incremented after each cycle. For the third cycle, the second state (220) performs a read/write operation and then transitions to a third state (230) that performs a read operation. As the processing transitions back to the second state (220), the address is decremented back to the initial address.
A second example of a test that is commonly performed is the Hammer 10 test, which isolates write recovery faults, illustrated in the flow chart of FIGS. 3a-d. As shown in FIG. 3a, the Hammer 10 test begins (Block 300) by writing a solid background of data to the cell being tested (Block 302). In one embodiment, a solid background of data is written by setting each bit at the memory address block to 0. The address block is set to the beginning X and Y coordinate, or (0,0), of the cell and a counter is set to 0 (Block 304). A read operation (Block 306), ten inverse write operations (Blocks 308, 310 and 312), and an inverse read operation (Block 314) are performed as the address coordinates are incremented until the maximum coordinates in the address block are reached. As illustrated in FIG. 3b, the address coordinates are set to zero for both the X and Y coordinates and the counter is reset to zero (Block 324). An inverse read operation (Block 326), ten write operations (Blocks 328, 330 and 332), and a read operation (Block 334) are performed as the address coordinates are incremented until the maximum coordinates in the address block are reached. As illustrated in FIG. 3c, the address coordinates are set at the maximum for both the X and Y coordinates and the counter is reset to zero (Block 344). A read operation (Block 346), ten inverse write operations (Blocks 348, 350 and 352), and an inverse read operation (Block 354) are performed as the address coordinates are decremented until the maximum coordinates in the address block are reached. As illustrated in FIG. 3d, the address coordinates are set to zero for both the X and Y coordinates and the counter is reset to zero (Block 364). An inverse read operation (Block 368), ten write operations (Blocks 368, 370 and 372), and a read operation (Block 374) are performed as the address coordinates are incremented until the maximum coordinates in the address block are reached, then the test is completed (Block 384).
A state machine to implement the Hammer 10 test is shown in the diagram of FIG. 4. The state machine includes an idle state (400) to which the state machine returns between test cycles and while tests are not being run. For the initial cycle in which a solid background is written, a first state (405) performs a looping write operation. With each write operation, the address is incremented until the entire memory cell has data written into it. For the second cycle, a second state (410) performs a read operation, in which data is read from an address, and then transitions to a third state (415) that performs a write operation, writing the inverted read data. Each of fourth state (420), fifth state (425), sixth state (430), seventh state (435), eighth state (440), ninth state (445), tenth state (450), eleventh state (455), and twelfth state (460) perform an additional write operation. The thirteenth state (465) performs a second read operation, at which the state machine transitions back to the second state (410). Again, the address is incremented after each cycle until the entire memory cell has had the cycle performed on it. For the third and fifth cycles, the same states as the second cycle are used, except that the first read operation is inverted, the repeated write operations are not inverted, and the final read operation is not inverted. The fourth cycle uses the same states as the second cycle, except that as the processing transitions back to the second state (410), the address is decremented back to the initial address.
As is shown by FIGS. 2 and 4, the state machines for even simple test suites like Mats++ and Hammer 10 quickly become complex. If a BIST was created to support all the various test suites, the state machine would be very complicated.